1. Field of the Invention
The present invention generally relates to the deposition of materials on a surface having severe topography, including the formation of patterns of potentially sub-lithographic dimensions and, more particularly, to particular arrangements for material deposition by sputtering especially for treatment of surfaces and fabrication of micromachines and semiconductor devices at high integration density.
2. Description of the Prior Art
In the field of integrated circuit and micromachine fabrication, many steps in highly complicated processes involve the removal or deposition of material and many techniques are known and widely practiced for the achievement of either result. In general, techniques for obtaining either result are classified as isotropic or anisotropic to indicate whether or not they can be expected to proceed in a preferred direction. Anisotropy can also be induced by convoluted surface topography with isotropic processing. Thus, in practice, most of these techniques, particularly for material deposition, are neither ideally isotropic nor ideally anisotropic. Deposition rates can also be significantly affected by the topography of the surface(s) on which deposition is to be performed, particularly in sputtering techniques where material is eroded from one surface (referred to as a target) and redeposited on another surface.
As is well-understood in the art, the rates of material deposition in sputtering processes are highly dependent on the angle of incidence of atoms or ions at the surface where deposition is to occur. That is, the likelihood of deposition of a particular atom or ion at a particular location on a surface increases as the angle of incidence approaches perpendicular to the surface at that location. Therefore, when the trajectories of sputtered particles are widely distributed, deposition will appear to be severely affected by surface formations and topographies which reduce the number of particles which reach particular regions of the surface. On the other hand, when the trajectories are confined, such as with collimation, deposition on surfaces substantially perpendicular to the particle trajectories as established by the collimation will be strongly preferred.
Severe surface topographies thus present substantial difficulties in obtaining desired deposits of material, whether the goal of the particular deposition process is uniformity of deposit thickness or high selectivity between surfaces on which deposits are to be formed. This problem is aggravated since, particularly at very small feature sizes comparable to minimum feature sizes available with current lithographic processes, the surface topography is dynamically changed by the thickness of the deposit as the deposition process is carried out.
More specifically, as integration densities have increased and feature sizes have decreased in integrated circuits, for example, it has become necessary to perform filling of relatively high aspect ratio (e.g. greater than 1:1 ratio of feature depth to transverse dimension of the feature) trenches or apertures in a substrate or layer. Isolation trenches and trench capacitors are examples of structures requiring such trench filling (generally with SiO.sub.2 and polysilicon, respectively) typically by chemical vapor deposition and other known techniques, including sputtering. However, chemical vapor deposition is currently considered to be much preferred over sputtering to fill severe topography for the reasons noted above. Similar high aspect ratio features and requirements for filling and/or deposition on severe topographies are also commonly encountered in micromachines.
Sputtering techniques are currently used principally for the deposition of metal for the formation of conductor patterns and collimation is known to improve deposition on severe topographies. However, collimation itself reduces the deposition rate of sputtered material, particularly on the recess (e.g. trench) sidewalls and develops an overburden or overhang at the top edges of the trench which causes non-uniformity across the bottom of the trench or aperture. In comparison, with uncollimated sputtering, the surface topography alters trajectory distribution of sputtered particles at different locations on a surface (hereinafter referred to as a "deposition surface" which may or may not feature severe topography as distinguished from the individual surfaces of particular features which may constitute severe topography of the deposition surface) which, in turn, causes deposition on trench or aperture sidewalls to proceed at a faster rate near the top of the trench, forming an overburden at the top of the trench, which similarly causes thinner and non-uniform deposition at the trench bottom and reduces the rate at which deposition occurs.
Further, with either collimated or uncollimated sputtering, because of deposition on sidewalls near the top of the trench or aperture, deposition in the corners of the bottom of the trench or aperture and in similarly shaped portions of severe surface topography is particularly compromised. When filling of trenches or apertures is attempted, these variations from uniformity of deposition may cause defects such as so-called keyhole voids within the incompletely filled trench or aperture. Layered structures, particularly for conductors crossing severe topography will also be formed with reduced thickness at a point where the surface orientation abruptly changes (e.g. from horizontal to vertical).
Perhaps more importantly, as integration density has increased, the "value" of surface area on the chip or features which may be formed thereon has increased and a technique to increase the usable area of a chip of given dimensions is critical to increased "device counts" for particular integrated circuit designs. In an attempt to accomplish such an effective increase in area where devices can be formed, several types of structures have been proposed but which require the ability to form substantially uniform deposits on surfaces which are at a large angle to the major dimension (e.g. deposition surface) of a wafer, such as the sidewalls of a trench or aperture. While collimated sputtering in a direction perpendicular to the wafer surface is known to favor deposition at the bottoms of such formations, sidewall deposition continues to be non-uniform.
Additionally, for maximum integration density of integrated circuits or the highest degree of miniaturization of micromachines, it is conventional to form at least some of the trenches and apertures or other features at or near the minimum feature size obtainable with the lithographic technology chosen for the design. Therefore, in such a case, any structure formed within the trench would be, necessarily, of sub-lithographic dimensions, at least for the same lithographic technology. Further, process complexity and cost increases dramatically for lithographic processes as minimum feature size is decreased. Criticality of registration is also increased and process tolerances reduced along with potential adverse impact on manufacturing yields.
Some techniques are known for production of so-called sub-lithographic feature sizes. A widely known technique, commonly referred to as sidewall image transfer (SIT), uses a combination of isotropic and anisotropic processes to form narrow sidewalls on a projecting feature, known as a mandrel, which may be later removed. (Similar topography is presented by a recessed feature, such as a trench, although trenches must remain in the structure of the design. Formations of the sidewalls of a trench are generally referred to as "spacers".) However, the sidewall structures can only be formed symmetrically in closed patterns on all sides of the feature (e.g. seen as pairs in the cross-section of a mandrel or trench). While closed patterns have found substantial utility in self-aligned semiconductor processes and can be modified with other lithographic processes such as masked etching, no process has existed for providing a single sub-lithographic pattern by sidewall image transfer. For example, the utility of angled sidewall deposition at an angle of 5.degree. to 25.degree. to the substrate surface in combination with angled impurity implantation is suggested for forming a field-effect transistor having an extremely short channel and gate alignment of improved accuracy in U.S. Pat. No. 4,532,698 to Frank F. Fang et al. which is assigned to the assignee of the present invention. However, the technique disclosed therein relies on the shallowness of the angle of deposition to minimize the thickness of deposition on horizontal surfaces so that any substrate deposition can be etched away without significant change of thickness of sidewall deposition and thus effectively assumes only a single vertical surface is available (at least within a distance which would severely limit integration density) for formation of a sidewall deposit.
In any case, known processes for carrying out SIT techniques are complicated and require close process tolerances. Further, SIT techniques may be compromised by non-uniform deposition on sidewall surfaces and/or variation from ideal anisotropy of etching applied to remove material other than that deposited on vertical surfaces, particularly when the sidewall deposit is reduced in thickness significantly below dimensions available with lithographic techniques.
Other applications such as micromachines also require structures which are of a geometry which may or may not have utility in integrated circuits. For example, a sub-lithographic T-shaped structure may provide benefits in electronic devices operating on vacuum tube rather than semiconductor principles for application in environments where strong electromagnetic fields may be encountered. Such a shape cannot be formed by sidewall image transfer since that process provides no selectivity between portions of the sidewall. Likewise, micromachine impellers may derive increased efficiency from particular shapes which cannot be formed by SIT techniques.
Numerous applications are also known where efficiency and/or degree of size reduction can be increased by surface treatments. For example, it is known that techniques which roughen the surface of material, such as the production of so-called hemispherical grains can increase the effective surface area and the capacitance value of capacitors of a fixed overall size. Other applications in which performance depends on increased surface area include but are not limited to solar-cells, material detectors, catalysts, fluid filters, and the production of porous surfaces, such as in some types of filters. Surface topography as well as area may also be of importance, for example, in optical or ultrasonic applications. Known surface treatment techniques are, however, somewhat limited in the amount of effective increase of surface area which can be achieved. For example, while still a highly significant improvement in capacitors, hemispherical grain provides an effective surface area increase which is limited to about 40%.
Some research has also been done in performing material deposition techniques at an angle. However, angled evaporation or sputtering has generally resulted in poor uniformity over large wafer areas required for economical throughput of semiconductor processing reactors. This problem has been attributed, in regard to uncollimated sputtering, to non-uniformities in the trajectories of particles ejected from the sputtering target which generally form lobes which are directed in dependence on grain orientation in the target. Even with collimated sputtering or attempts to exploit preferred angles of particle ejection from a sputtering target, directivity of the particles toward the deposition surface on which material is to be deposited may be lost over distances as short as about two centimeters, limiting the area which can receive relatively uniform deposition as distance from the sputtering target varies.
It should also be noted that collimated sputtering for filling of trenches, apertures and other severe surface topography and angular deposition techniques as practiced to date have been mutually exclusive processes. Collimation requires use of a collimation grid generally having apertures with an aspect ratio of 1:1 or greater (although lower aspect ratios may be used for some applications when necessitated by a trade-off between deposition rate and degree of particle directivity) and limits the angular distribution of trajectories of particle to be deposited. Such limitation of the angle of particle trajectories would require a substantial distance from the target to the wafer if a collimation grid were to be applied to the target during angled sputtering in order to obtain coverage for the transverse dimension of the wafer surface. If the deposition surface is inclined to the sputtering target and the direction of collimation of the collimation grid as has generally been done, substantial differences in distance from the sputtering target to the deposition surface will be presented at different locations on the deposition surface.
For this reason, collimated sputtering is principally performed only in a direction perpendicular to the deposition surface on which material is to be deposited, often with a grid formed with hexagonal cells in a "honeycomb" pattern for collimation over the wafer surface since such a collimator may be placed close to the surface. Accordingly, no technique is currently available which can favor deposition on sidewalls of upright formations, uniformly provide angled material deposition, form substantially uniform depositions on vertical sidewalls over the surface of a wafer or provide selectivity between portions of sidewalls.